CAD Engineer

  Aquantia Semiconductor India Private Limited

 India, IN

Job Requirement Details

Job Categories

  • it-hardware & networking

Functional Areas

  • Engineering Design / R&D

Key Skills

  • Analog
  • C
  • C++
  • Cad
  • Digital Signal Processing
  • Perl Scripting
  • Vlsi


  • B.E In Electrical & Electronics
  • B.Tech/B.E.
  • M. Tech

Other Details

Experience Level

3 Years - 5 Years

Job Type


Shift Time

Full Time - Morning

Job Description

Candidate must be an experienced CAD/EDA engineer able to develop and enhance state-of-art Analog and mixed-signal design methodologies for advanced technology nodes to enable efficient design and development of products.

The candidate would also establish collaboration with EDA vendors and work with circuit & layout design community to facilitate implementation and support of these flows.

A CAD engineer who has an urge on the pulse of latest tools and programming techniques and methodologies.

The candidate is not just looking to “support” CAD infrastructure but looking to enhance efficiencies and have meaningful and measurable impact of development speed and time to market.

The candidate must exhibit good communications, attitude and professional relationships with various team members.

  • BSEE/MSEE with minimum 3 years of relevant experience.
  • Good understanding of process technologies and device physics.
  • Good understanding of transistor level analog circuit simulation tools.
  • Good understanding of Digital & Analog Layout.
  • Good awareness of VLSI flow methodology RTL->GDS.
  • Good awareness of various CAD tools including Front-End, Verification & Back-End.
  • Good experience of Place & Route tools (PNR/P&R) like ICC, Encounter & Innovus etc…
  • Hands on experience of Cadence Schematic & Layout tools including ADEL/XL, Layout-XL.
  • Hands on experience of physical verification tools like Cadence-PVS, Mentor-Calibre etc.
  • Hands on experience with GDS tools like Calibre-DRV and/or QuickView(k2_viewer).
  • Good understanding of physical verification ruledecks which uses PVL/SVRF.
  • Good understanding of PDKs of various technologies ex: TSMC, GF, IBM, Intel etc…
  • Good knowledge of Cadence-SKILL language.
  • Good experience with programming languages like C, C++ and/or LISP etc…
  • Solid knowledge of scripting languages like PERL, TCL, Shell (bash/ksh/tcsh) and/or Python, Ruby.
  • Hands on experience in developing Graphical User Interfaces(GUIs) using Perl-TK/TCL-TK/Python-TK/Ruby-TK etc…
  • Hands on experience with DRC/LVS/PEX flow methodologies including development & debugging.
  • Good awareness of Power/EMIR tools like Apache-Totem/Voltus etc..
  • Experience in development, maintenance and support of CAD environments for IC designs.
  • Firm understanding of Cadence DFII.

How To Apply

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